Method and device for managing multi-frames

ABSTRACT

A device includes a processor and a time slot assigner, connected to a communication line via a physical layer unit. The physical layer unit is adapted to generate a communication line clock signal and a multi-frame synchronization signal. The device also includes a transmit media access controller (MAC) adapted to receive the multi-frame synchronization signal and the communication line clock signal and in response to scan, during a single multi-frame transmission period, multiple transmit MAC memory entry groups such as to retrieve transmission instructions and in response to enable access to the communication line. During a single multi-frame transmission period the transmit MAC accesses at least twice at least one transmit MAC memory entry group. The processor receives a processor clock signal that differs from the communication line clock signal. The MAC also performs reception operations using receive clock and sync signals.

FIELD OF THE INVENTION

The invention relates to a device having multi-frame managementcapabilities and to a method for multi-frame management.

BACKGROUND OF THE INVENTION

In today's telecommunications, digital networks transport large amountsof information. Network services can be, for example, traditional voicephone, facsimile, television, audio and video broadcast, and datatransfer.

With the increasing need of information exchange in the global society,the capacity of existing and future networks must be used efficiently.Multiplexers switch different network services to a single network insuch a way that every service is fully maintained and does not disturbother services.

Communication integrated circuits use various techniques, such as timedivision multiplexing (TDM), to transmit information from multiplecommunication channels over a single communication line, as well as toreceive information the is destined to many communication channels.

Exemplary communication integrated circuits and TDM methods areillustrated in U.S. Pat. No. 6,771,630 of Weitz et al., and U.S. Pat.No. 6,167,059 of Hagai et al., both being incorporated herein byreference. An exemplary TDM scheme is illustrated in U.S. Pat. No.4,855,996 of Douskalis.

The multiple communication channels are organized in frames. Simple TDMframes are just duplicated over time. Thus, the content of a certainframe (the allocation of time slots within the frame) remains the sameover long periods. Recently, there is a need to define multi-frames thatare characterized by including repetitions of multiple different frames.

These multi-frames are usually transmitted or received over channelsthat require highly accurate time division multiplexing andsynchronization.

There is a need to provide efficient methods for multi-frame managementand to provide a device having multi-frame management capabilities.

SUMMARY OF THE PRESENT INVENTION

A device having multi-frame management capabilities and a method formanaging multi-frames.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood and appreciated more fully fromthe following detailed description taken in conjunction with thedrawings in which:

FIG. 1 illustrates a device, according to an embodiment of theinvention;

FIG. 2 illustrates a device according to another embodiment of theinvention;

FIG. 3 illustrates a communication engine, according to an embodiment ofthe invention;

FIG. 4 illustrates a transmit media access controller, according to anembodiment of the invention;

FIG. 5 illustrates a transmit media access controller, according toanother embodiment of the invention;

FIG. 6 is a timing diagram according to an embodiment of the invention;

FIG. 7 is a flow chart of a method for transmitting multi-frames,according to an embodiment of the invention;

FIG. 8 illustrates various stages of the method for transmitting ofmulti-frames, according to an embodiment of the invention;

FIG. 9 illustrates a receive media access controller, according toanother embodiment of the invention;

FIG. 10 is a flow chart of a method for receiving multi-frames,according to an embodiment of the invention; and

FIG. 11 illustrates various stages of the method for receivingmulti-frames, according to an embodiment of the invention.

DETAILED DESCRIPTION OF THE DRAWINGS

The invention provides a device having multi-frame managementcapabilities and a method for managing multi-frames. The device cancontrol (manage) the transmission and/or the reception of multi-frames.

According to an embodiment of the invention the device includes one ormore processors that are adapted to generate transmission instructionsand/or reception instructions. The one or more processors are usuallynot synchronized with the communication line, but a media accesscontroller is synchronized with the communication line and can executetransmission and/or reception instructions that enable the transmissionand/or reception of multi-frames. Transmission instructions areorganized in transmit MAC memory entry groups, whereas each group storestransmission instructions that control a transmission of a frame. Amulti-frame is transmitted by scanning multiple transmit MAC memoryentry groups, while at least one transmit MAC memory entry group isscanned multiple times during a single multi-frame period.

Reception instructions are organized in receive MAC memory entry groups,whereas each group stores reception instructions that control areception of a frame. The reception process defined which receivedsignals belong to which communication channel. A multi-frame is receivedby scanning multiple receive MAC memory entry groups, while at least onereceive MAC memory entry group is scanned multiple times during a singlemulti-frame period.

Conveniently, transmit and/or receive MAC memory entry groups may belocated in a time slot assigner in order to allow the interleaving ofdata from multiple media access controllers.

According to an embodiment of the invention the transmission ofmulti-frames is executed by components that also receive multi-frames.It is noted that different clock signals (as well as synchronizationsignals) can be used for transmission and reception, that the samecommunication line can convey bi-directional traffic, but this is notnecessarily so.

For simplicity of explanation most of the following description refersto transmission of multi-frames although it can be applied mutatismutandis to reception of multi-frames. For example, various signals thatare mentioned below (such as MFRAME_TX_SYNC1, MFRAME_TX_SYNC2,LINE_TX_CLK1, LINE_TX_CLK2) are used to clock transmission paths and tosynchronize the transmission of multi-frames. Conveniently, other(analogues) signals are used to synchronize and to clock receptionpaths. These latter signals (such as LINE_RX_CLK1, MFRAME_RX_SYNC1 andIFRAME_RX_SYNC1) are illustrated only in FIG. 9, for convenience ofexplanation.

It is further noted that the number of synchronizing signals and clocksignals can be responsive to the number of ports that are controlled bythe device. For example, if a certain media access controller controlseight TDM ports then one till eight different clocking and multi-framesynchronizing signals can be used in each direction, for example, in aneight TDM line configuration, up to 16 at a whole.

It is noted that a single media access controller can operate both as atransmit media access controller and as a receive media accesscontroller but this is not necessarily so. In addition the reception andtransmission can occur in parallel to each other or in a sequentialmanner.

According to an embodiment of the invention the device includes aprocessor and is connected to a communication line via variouscomponents such as a physical layer unit. The physical layer unit isadapted to generate a communication line transmission clock signal(LINE_TX_CLK1 191) and a multi-frame transmission synchronization signal(MFRAME_TX_SYNC1 192). The device further includes a media accesscontroller (also referred to as a time slot assigner) that is connectedto the physical layer unit via a time slot assigner that may be therouting element. The media access controller is adapted to receiveMFRAME_TX_SYNC1 192 and LINE_TX_CLK1 191 and in response to scan, duringa single multi-frame period, multiple transmit MAC memory entry groupssuch as to retrieve transmission instructions and in response to enableaccess to the communication line. Each transmit MAC memory entry groupstores transmission instructions that control the transmission of aframe. During a single multi-frame transmission period the MAC accessesmultiple times one or more transmit MAC memory entry groups. Theprocessor is adapted to generate the multiple transmission instructionsand is also adapted to receive a processor clock signal PR_CLK thatdiffers from LINE_TX_CLK1.

FIG. 1 illustrates a device 10, according to an embodiment of theinvention.

The device 10 is adapted to assemble and disassemble time divisionmultiplexed (TDM) lines. Device 10 is adapted to use routing tables inorder to support a large number of TDM lines.

Device 10 includes two RISC processors 220 and 222, a shared data RAMmemory unit 230, a shared instruction RAM memory unit 232, direct memoryaccess (DMA) controller 210, multiple receive and transmit MAC layerunits (also referred to as MAC units) 40-48, multiple receive andtransmit memory units 90-98 and associated access logics 50-58.

The first and second RISC processors 220 and 222 can access the shareddata RAM memory unit 230 and a shared instruction RAM memory unit 232.These RISC processors can be accessed using schedulers (not shown), butthis is not necessarily so.

The first RISC processor 220 is connected to a first hardwareaccelerator 223 and to multiple receive and transmit memory units 90-98.The second RISC processor 222 is connected to a second hardwareaccelerator 224 and to multiple receive and transmit memory units 90-98.The hardware accelerators 223 and 224 can perform various mathematicalfunctions such as searching for a match within a small memory entrygroup, finding a maximum value or a minimum value within an array ofnumber and the like. These accelerators are optional.

According to an embodiment of the invention the device can includeprocessors that are not RISC processors, instead of RISC processors 220and 222.

Conveniently, both RISC processors 220 and 222 receive the same clocksignal PR_CLK, but this is not necessarily so. These RISC processorsusually manage multiple tasks and communicate with multiple componentsof device 10. Usually, neither one of RISC processors 220 and 222 issynchronized with the clock of each communication line connected todevice 10.

According to an embodiment of the invention the first RISC processor 220is connected to receive memory units 90 and 92 and to transmit memoryunits 91 and 93. The second RISC processor 222 is connected to receivememory units 95 and 97 and to transmit memory units 96 and 98. The RISCprocessors 220 and 222 can operate independently from each other, butthey can also cooperate with each other thus sharing the MAC units andcan controlling them together.

Receive memory units such as units 90, 92, 95 and 97 receive datasegments and data segment write requests from data sources. They decidewhich data segments to provide to the RISC processors 220 and 222. Thedata segments are eventually read by RISC processors 220 and 222. Thereceive memory units can receive status information from data sources.This status information can be related to data to be transmitted fromdevice 10 to data targets.

Receive memory unit 90, access logic 50 and MAC unit 40 form firstreception path 281. Receive memory unit 92, access logic 52 and MAC unit42 form second reception path 282. Transmit memory unit 91, access logic51 and MAC unit 41 form a first transmission path 211. Transmit memoryunit 93, access logic 53 and MAC unit 43 form a second transmission path212.

The first and second transmission paths 211 and 212 and the first andsecond reception paths 281 and 282 are connected to time slot assigner264. These paths are connected to physical layer unit 290 via additionalcomponents that are not illustrated in FIG. 1 (such as communicationinterfaces and ports).

The physical layer unit 290 is connected to communication line 20. Thephysical layer unit 290 can be included within device 10 but this is notnecessarily so. It is noted that each path can be connected to aseparate physical layer unit, or that a pair of paths can be connectedto a physical layer unit. It is further noted that a physical layer unitis usually connected to one or more reception path as well as to one ormore transmission path.

The physical layer unit 290 sends MAC units 41 and 43 a communicationline clock signal LINE_TX_CLK1 191 that is used to synchronize thetransmission from device 10 to the communication line 20. The physicallayer unit 290 also sends a multi-frame synchronization signalMFRAME_TX_SYNC1 that indicates that a multi-frame should be transmitted.

Time slot assigner 264 can perform time division multiplexing betweenthe transmission paths that are connected to it.

Receive memory unit 95, access logic 55 and MAC unit 45 form a thirdreception path 285. Receive memory unit 97, access logic 57 and MAC unit47 form a fourth reception path 286. Transmit memory unit 96, accesslogic 56 and MAC unit 46 form a third transmission path 215. Transmitmemory unit 98, access logic 58 and MAC unit 48 form a fourthtransmission path 216.

The third and fourth transmission paths 215 and 216 and the third andfourth reception paths are connected to second time slot assigner 266.These paths are connected to second physical layer unit 292 viaadditional components that are not illustrated in FIG. 1 (such ascommunication interfaces and ports). It is noted that each path can beconnected to a separate physical layer unit, or that a pair of paths canbe connected to a single physical layer unit.

Every MAC unit has an internal memory unit and includes an internalmemory unit that can store channel information from multiplecommunication channels. These MAC units are also adapted to receivetransmission instructions from time slot assigner 264 and in responseenable the transmission of information from the transmission paths thatare connected to it, same for reception.

FIG. 2 illustrates a communication device 10, according to an embodimentof the invention.

Communication device 10 includes a general-purpose processor 180, asecurity engine 170, system interface unit 140, communication engine 200and multiple ports (not shown). Components 180, 170, 140 and 200 areconnected to each other by central bus 190.

The general-purpose processor 180 can include multiple execution unitssuch as but not limited to an integer unit, a branch processing unit, afloating point unit, a load/store unit and a system register unit. Itcan also include various cache memories, dynamic power management unit,translation look aside buffers, and the like.

The general-purpose processor 180 controls the communication device 10and can execute various programs according to the required functionalityof communication device 10. The general-purpose processor 180 can be amember of the PowerPC™ family but this is not necessarily so.

The security engine 170 can apply various security mechanisms includingencryption based mechanisms and the like.

Communication device 10 can be connected to multiple memory units aswell as other components. These components are interfaced by systeminterface unit 140. System interface unit 140 may include some of thefollowing components: external memory controllers 142, external DDRinterface unit 144, PCI bridge 146, local bus 148, bus arbitrator 150,Dual UART unit 152, dual 12C unit 154, a four channel DMA 156, interruptcontroller 158, protection and configuration unit 160, system reset unit162 and clock synthesizer 164. It is noted that other interfacingcomponents can be used.

FIG. 3 illustrates a communication engine 200, according to anembodiment of the invention.

It is noted that FIG. 3 illustrates an embodiment of the invention andthat other communication engines (including those who have a singleprocessor or more than two processors) can be used.

The communication engine 200 is a versatile communication component thatcan manage multiple communication ports that operate according todifferent communication protocols.

The communication engine 200 includes two RISC processors 220 and 222,DMA controller 210, a shared data RAM memory unit 230, a sharedinstruction RAM memory unit 232, eight universal communicationcontrollers denoted UCC1-UCC8 241-248, one multi-channel communicationcontroller (MCC) 251, two serial peripheral interfaces denoted SP1-SP2252-253, two UTOPIA POS controllers 261 and 262, two time slot assigners264 and 266 and two communication interfaces 270 and 274. Time slotassigner 264 assigns time slots for accessing communication interface270. Time slot assigner 266 assigns time slots for accessingcommunication interface 274.

Each communication controller out of communication controllersUCC1-UCC8, MCC, and SPI1-SP2 can include transmission paths such astransmission paths 211, 212, 215 and 216 as well as reception paths suchas reception paths 281, 282, 285 and 286. This is done by a connectionmade from Time Slot Assigner 264 to Time Slot Assigner 266. In thesecond embodiment of the communication controller there is support for 8TDM lines instead of 4 in the first embodiment of device 10, the numbercan be altered in any architecture.

Conveniently, UCC1 241, UCC3 243, UCC5 245 and UCC7 247 can becontrolled by UTOPIA POS controller 260, and that these controllers aswell as MCC 251 can access the communication interface 270 (andeventually communication line 20) in response to transmissioninstructions sent by time slot assigner 264. It is further noted thatsome of these controllers can selectively bypass the time slot assigner264.

Conveniently, UCC2 242, UCC4 244, UCC6 246 and UCC8 248 can becontrolled by UTOPIA POS controller 262, and that these controllers canaccess the second communication interface 274 (and eventually secondcommunication line 22) in response to transmission instructions sent bytime slot assigner 266. It is further noted that some of thesecontrollers can selectively bypass the time slot assigner 266 but arealso connected to Time slot assigner 264 so they will be to be connectedto TDM ports 271.

The first communication interface 270 is connected to multiple timedivision multiplex (TDM) ports that are collectively denoted 271, aUTOPIA-packet over SONET (POS) port 272, as well as four RMII portscollectively denoted 273, and four NMSI ports collectively denoted 274.

The second communication interface 274 is connected to anotherUTOPIA-packet over SONET (POS) port 275, four RMII ports collectivelydenoted 276, and four NMSI ports collectively denoted 274. It is notedthat other communication protocols can be supported by communicationdevice 10.

Conveniently, a UCC can support the following communication protocolsand interfaces (not all simultaneously): 10/100 Mbps Ethernet, 1000 MpbsEthernet, IPv4 and IPv6, L2 Ethernet switching using, ATM protocol viaUTOPIA interface, various types of HDLC, UART, and BISYNC.

Conveniently, MCC 251 supports two hundred and fifty six HDLC ortransparent channels, one hundred and twenty eight SS#7 channels ormultiple channels that can be multiplexed to one or more TDM interfaces.

In addition, the communication engine 200 can include a controller (notshown) as well as an interrupt unit that coordinate the variouscomponents of the communication engine, as well as to enable thecommunication engine 200 to communicate with general-purpose processor180, security engine 170 and system interface unit 140.

Time slot assignor 264 receives LINE_TX_CLK1 191 and MFRAME_Tx_SYNC1 192from the physical layer unit 290. Time slot assignor 266 receivesLINE_TX_CLK2 197 and MFRAME_TX_SYNC2 198 from the physical layer unit292.

Conveniently the both time slot assigners are connected to each other.This can allow UCC2 242, UCC4 244, UCC6 246 and UCC8 248 to access thefirst communication line 20.

Conveniently the multi-frame synchronization signals and the clocksignals can be a common signal or per TDM, independent or common forreceive and/or transmit.

FIG. 4 illustrates a transmit media access controller 264′, according toan embodiment of the invention.

Transmit media access controller 264′ can be included within time slotassigner 264. The time slot assigner 264 can include additional circuitssuch as but not limited to a media access control circuit that controlsthe reception of information from the communication line 20.

Media access controller 264′ receives MFRAME_TX_SYNC1 192 andLINE_TX_CLK1 191 and in response scans, during a single multi-frametransmission period, multiple transmit MAC memory entry groups150(1)-150(K) such as to retrieve transmission instructions and inresponse to enable access to the communication line. Each transmit MACmemory entry group 150(k) stores transmission instructions that controla transmission of a frame. During a single multi-frame transmissionperiod the transmit media access controller 264′ accesses at least twiceone or more transmit MAC memory entry group.

Transmit media access controller 264′ includes a transmit memory unit150, a transmit control circuit 110, multiple transmit frame accesscircuits 120(1)-120(K), a transmission controller 160 and an end ofgroup indicator (EOGI) detector 140.

The transmit control circuit 110 is connected to the multiple transmitframe access circuits 120(1)-120(K), and to the transmit memory unit150. The transmit control circuit 110 scans, during a single multi-frametransmission period, multiple transmit MAC memory entry groups150(1)-150(K). The retrieved transmission instructions are sent to EOGIdetector 140 and to transmission controller 160.

Each transmit MAC memory entry group 150(k) stores transmissioninstructions that control a transmission of a frame. Index k rangesbetween 1 and K, whereas K represents the number of different framesthat are included within a multi-frame. For simplicity of explanationonly two transmit MAC memory entry groups are illustrated (the first andthe K'th transmit MAC memory entry groups) but K can exceed two.

A typical transmit frame access circuits (120(k)) out of circuits120(1)-120(K) is adapted to repetitively generate a media memory unitaddress sequence that corresponds to the address of entries that form anassociated transmit MAC memory entry group (150(k)). The transmitcontrol circuit 110 is adapted to select between the multiple transmitframe access circuits 120(1)-120(K).

Conveniently, each transmit MAC memory entry group (150(k)) ends by anend of group indicator (EOGI) and the EOGI detector 140 can detect anEOGI and in response notifies the transmit control circuit 110. Transmitcontrol circuit 110 can receive this indication as well as otherindications and can determine which is the next transmit MAC memoryentry group to scan.

First transmit frame access circuit 120(1) includes a first transmit MACentry group address register 121(1) that stores the address of the firstentry of the first transmit MAC memory entry group 150(1). This addressis sent to the transmit control circuit 110 whenever the transmitcontrol circuit 110 starts to scan the first transmit MAC memory entrygroup 150(1). The transmit control circuit 110 scans the first transmitMAC memory entry group by 150(1) incrementing the addresses until theEOGI detector 140 detects that the end of the first transmit MAC memoryentry group 150(1) was reached. Once it occurs the first repetitioncounter 123(1) updates its value to reflect that the first MAC entrygroup was scanned. The inventors used a count down counter that itscontent was compared to zero (by zero detector 122(1)) to indicate thata predefined number of scans of the first transmit MAC memory entrygroup was completed. Once the predefined number of scans is completedthe first repetition counter 123(1) is updated to the initial predefinedrepetition number.

When the predefined number of scans of the first transmit MAC memoryentry group 150(1) is completed the second transmit frame access circuit120(2) is selected, and so on, until the K'th transmit frame accesscircuit 120(K) is selected by the transmit control circuit 110, and theK'th transmit MAC memory entry group 150(K) is scanned for a predefinednumber of times. After the K'th transmit MAC memory entry group 150(K)is scanned for a predefined number of times the transmission of themulti-frame ends and the transmit media access controller 264′ waits toreceive the next MFRAME_TX_SYNC1 192.

The memory outputs transmission instructions to the EOGI detector 140and to transmission controller 160. The EOGI detector 140 looks for theEOGI field, while the transmission controller 160 sends transmissioninstructions to the transmission controller 160. The transmissioncontroller 160 sends transmission instructions to transmission pathssuch as paths 211-214 and in response these transmission paths transmitinformation towards the physical layer unit 290. For simplicity ofexplanation communication interface 170 and TDM ports 271 were omittedfrom FIG. 5.

It is noted that the transmission instructions sent to transmissioncontroller 160 can differ from the transmission instructions sent by thetransmission controller 160 to the transmission paths. For example, ifthe transmission controller 160 is connected to each transmission pathvia a dedicated control line the transmission instructions sent by thetransmission controller 160 to the transmission paths do not necessarilyinclude transmission path identification information while convenientlythe transmission instructions sent to the transmission controller 160include such information. It is further noted that the changes canresult from differences in the format of the transmission instructions.The transmission controller 160 can send only one transmissioninstruction at a time but this is not necessarily so. The transmissioninstructions can include transmission start time information, althoughthis is not necessarily so. Conveniently, a transmission instructiondefines the time slot allocated to each transmission path.

According to an embodiment of the invention a scanning of a transmit MACmemory entry group is synchronized by a synchronization signalMFRAME_TX_SYNC.

FIG. 5 illustrates a transmit media access controller 266′, according toanother embodiment of the invention.

Transmit media access controller 266′ can be included within time slotassigner 266. The time slot assigner 266 can include additional circuitssuch as but not limited to a media access control circuit that controlsthe reception of information from the communication line 20.

Transmit media access controller 266′ is connected to transmission paths215-218 that are connected (via at least one component) to physicallayer unit 292.

Transmit media access controller 266′ resembles transmit media accesscontroller 264′. Both can operate at the same manner, independently fromeach other and in parallel to each other.

Media access controller receives LINE_TX_CLK2 197, MFRAME_TX_SYNC2 198and optionally IFRAME_TX_SYNC2 199′.

Transmit media access controller 266′ is also referred to as secondtransmit media access controller or second transmit MAC 266′. Itincludes a second transmit MAC memory unit 150′, a second transmitcontrol circuit 110′, multiple transmit frame access circuits120′(1)-120′(K), a second transmission controller 160′ and a second endof group indicator (EOGI) detector 140′.

FIG. 6 is a timing diagram of a transmission sequence, according to anembodiment of the invention.

For convenience of explanation it is assumed that K equals two, and thata multi-frame includes three repetitions of a first frame that isfollowed by two repetitions of a second frame. The first transmit memoryentry group 150(1) stores transmission instructions that control thetransmission of the first frame while a second transmit memory entrygroup 150(2) stores transmission instructions that control thetransmission of the second frame.

It is further assumed that the transmission of the first frame is fourclock cycle long while the transmission of the second frame is six clockcycles long. It is noted that the frames are usually much longer.

At a first cycle (CS1) of LINE_TX_CLK1 191 a multi-frame transmissionstarts, as indicated by the assertion of MFRAME_TX_SYNC1 192.

The value 193 of the first repetition counter 123(1) equals two, whilethe value 194 of the second repetition counter 123(2) equals one. Thetransmit control circuit 110 scans the first transmit MAC memory entry150(1). The first scan of the first transmit MAC memory entry group150(1) ends at the fourth clock cycle (CS4) of LINE_TX_CLK1 191, and atthe following clock cycle (CS5) the value 193 of the first repetitioncounter 123(1) equals one. This indicates that the second scan of thefirst Transmit MAC memory entry group 150(1) is in progress.

The second scan of the first Transmit MAC memory entry group 150(1) endsat the eighth clock cycle of LINE_TX_CLK1 191, and at the followingclock cycle (CS9) the value 193 of the first repetition counter 123(1)equals zero. This indicates that the third and last scan of the firsttransmit MAC memory entry group 150(1) is in progress.

The third scan of the first transmit MAC memory entry group 150(1) endsat the twelfth clock cycle of LINE_TX_CLK1 191, and at the followingclock cycle (CS13) the value 193 of the first repetition counter 123(1)equals two. The value 194 of the second repetition counter 123(2) equalsone. This indicates that the first scan of the second transmit MACmemory entry group 150(2) is in progress.

The first scan of the second transmit MAC memory entry group 150(2) endsat the eighteenth clock cycle of LINE_TX_CLK1 191, and at the followingclock cycle (CS19) the value 194 of the second repetition counter 123(2)equals zero. This indicates that the second scan of the second TransmitMAC memory entry group 150(2) is in progress.

The second scan of the second transmit MAC memory entry group 150(2)ends at the twenty fourth clock cycle of LINE_TX_CLK1 191, and at thefollowing clock cycle (CS25) a new MFRAME_TX_SYNC1 192 is received andthe first Transmit MAC memory entry is scanned. The value 194 of thesecond repetition counter 123(2) is updated to one.

The value 193 of the first repetition counter 123(1) equals two, whilethe value 194 of the second repetition counter 123(2) equals one. Thecontrol circuit 110 scans the first Transmit MAC memory entry 150(1).The first scan of the first Transmit MAC memory entry group 150(1)(during the second multi-frame) ends at the twenty eighth clock cycle ofLINE_TX_CLK1 191, and at the following clock cycle (CS29) the value 193of the first repetition counter 123(1) equals one. This indicates thatthe second scan of the first Transmit MAC memory entry group 150(1) isin progress.

FIG. 7 is a flow chart of method 300 for transmitting multi-frames,according to an embodiment of the invention.

Method 300 starts by stage 310 of providing a processor clock signalPR_CLK 196 to a processor and providing a communication line transmitclock signal LINE_TX_CLK1 191 to a transmit media access controller,such as transmit media access controller 264′.

Stage 310 is followed by stage 330 of writing, to the transmit mediaaccess controller, multiple transmission instructions that control atransmission of a multi-frame. These transmission instructions definetime windows allocated to transmitters.

Stage 330 is followed by stages 350 and 360.

Stage 350 includes scanning, during a single multi-frame transmissionperiod (that conveniently starts by a transmit multi-framesynchronization signal MFRAME_TX_SYNC1), multiple transmit MAC memoryentry groups such as to retrieve transmission instructions. A transmitMAC memory entry group stores transmission instructions that control atransmission of a frame. During a single multi-frame transmission periodone or more transmit MAC memory entry groups are scanned multiple times.

Conveniently, stage 350 includes stage 352 of repetitively selecting aselected transmit frame access circuit out of multiple transmit frameaccess circuit. Each transmit frame access circuit is adapted torepetitively generate a transmit MAC memory unit address sequence thatcorresponds to address of entries of an associated Transmit MAC memoryentry group. Stage 352 is followed by stage 354 of scanning, in responseto information provided by the selected transmit frame access circuit, aselected transmit MAC memory entry group.

Conveniently, stage 350 includes searching for an end of group indicator(EOGI) indicative of an end of a currently scanned MAC entry group, anddetermining a next scanned Transmit MAC memory entry group in responseto the detection of the EOGI.

Conveniently, stage 350 includes timing a scanning of at least onetransmit MAC memory entry group in response to a reception of anintra-multi-frame transmit synchronization signal such asIFRAME_TX_SYNC1 199 and detection of the EOGI.

Stage 360 includes enabling, in response to the retrieved transmissioninstructions, access to the communication line.

Conveniently, stage 360 includes sending transmission commands tomultiple transmission paths (also referred to as transmitters) andconveying information provided by the multiple transmitters to thecommunication line.

Conveniently, stage 310 also includes providing a processor clock signalPR_CLK 196 to a second processor and providing a second communicationline transmit clock signal LINE_TX_CLK2 197 to a second transmit mediaaccess controller. Stage 330 of writing further includes writing to thesecond transmit media access controller, multiple transmissioninstructions that control a transmission of a second multi-frame. Stage350 of scanning further includes scanning, during a single multi-frametransmission period that starts by a second multi-frame synchronizationtransmit signal MFRAME_TX_SYNC2 198, multiple second transmit MAC memoryentry groups such as to retrieve transmission instructions. Stage 360further includes enabling, in response to the retrieved transmissioninstructions, access to a second communication line. A second TransmitMAC memory entry group stores transmission instructions that control atransmission of a frame. During single multi-frame period the scanningincludes scanning at least twice at least one Transmit MAC memory entrygroup.

FIG. 8 illustrates various stages 350, 360 of method 300 fortransmitting multi-frames, according to an embodiment of the invention.

Stage 350 starts by stage 371 of receiving MFRAME_TX_SYNC1 192 andselecting a first selected Transmit MAC memory entry group. Index k andindex j are set to one. These indexes are used to repetitively scan thevarious Transmit MAC memory entry groups of the Transmit MAC memoryunit. It is noted that index k can be set to another value, but it isassumed, for simplicity of explanation that the memory unit 150 isarranged such that the Transmit MAC memory entries groups are arrange incorrespondence to the transmission order, thus simplifying the jumpprocess between the different Transmit MAC memory entry units andsimplifying the determination of when the scan process ends.

Stage 371 is followed by stage 373 of reading the j'th entry of the k'thTransmit MAC memory entry group in synchronization with LINE_TX_CLK1 191and providing it to a transmission controller. The accessed entryincludes a transmission instruction that is sent to the transmissioncontroller.

Stage 373 is followed by stages 375 and 361. Stage 375 includesdetermining if the j'th entry is the last entry of the k'th Transmit MACmemory entry group. If the answer is negative stage 375 is followed bystage 376 of increasing index j: j=j+1. Stage 376 is followed by stage373. Stages 373-376 scan the entire k'th Transmit MAC memory entrygroup.

If the answer is positive (the j'th entry of the k'th Transmit MACmemory entry group is the group) then stage 375 is followed by stage 377of setting index j to one. Stage 377 is followed by stage 379 ofdetermining whether to update k. The update can be responsive to theamount of repetition of the k'th frame that still needs to betransmitted. If index k is not updated then the previously scannedTransmit MAC memory entry group is scanned again. If the answer ispositive then index k is updated. It is noted that non-consecutiveordering of the Transmit MAC memory entry groups can cause index k to beupdated in other manners. Assuming that there are K different frameswithin the multi-frame then k is updated such that after the K'th framesindex k returns to one. This is illustrated by using a modulo operation:k=Mod_(K)|k+1|.

Stage 381 is followed by stage 383 of determining if the multi-frametransmission ended. If the answer is positive then stage 383 is followedby stage 371, else it is followed by stage 373.

Stage 373 is followed by stage 361 of providing the retrievedtransmission instruction to a selected transmitter (or transmissionpath) out of multiple transmitters (or transmission paths) and stage 363of transmitting information in response to the transmission instruction,by the selected transmitter. Stage 363 is followed by stage 383.

According to an embodiment of the invention the scanning of a TransmitMAC memory entry group can be synchronized with timing signals such asintra-multi-frame synchronization signal IFRAME_TX_SYNC 199. Thus,stages 379 and 381 may be followed by stage 373 only after such asynchronizing signal is received. It is noted that the transmission ofeach frame can be synchronized but this is not necessarily so.

FIG. 9 illustrates a receive media access controller 264″, according toan embodiment of the invention.

Receive media access controller 264″ can be included within time slotassigner 264. The time slot assigner 264 can include additional circuitssuch as but not limited to a media access control circuit that controlsthe transmission of information to the communication line 20.

Receive media access controller 264″ receives MFRAME_RX_SYNC1 192″ thatindicates that a reception of a multi-frame starts and is clocked by areception communication line clock LINE_RX_CLK1″ 191″. In response tothese signals the receive media access controller 264″ scans, during asingle multi-frame period, multiple receive MAC memory entry groups150″(1)-150″(K) such as to retrieve reception instructions and inresponse to control the reception of information from the communicationline. Each receive MAC memory entry group 150″(k) stores receptioninstructions that control a reception of a frame. During a singlemulti-frame reception period the receive media access controller 264″accesses at least twice one or more receive MAC memory entry group.

Receive media access controller 264″ includes a receive memory unit150″, a receive control circuit 110″, multiple receive frame accesscircuits 120″(1)-120″(K), a reception controller 160″ and an end ofgroup indicator (EOGI) detector 140″.

The receive control circuit 110″ is connected to the multiple receiveframe access circuits 120″(1)-120″(K), and to the receive memory unit150″. The receive control circuit 110″ scans, during a singlemulti-frame reception period, multiple receive MAC memory entry groups150″(1)-150″(K). The retrieved reception instructions are sent to EOGIdetector 140″ and to reception controller 160″.

Each receive MAC memory entry group 150″(k) stores receptioninstructions that control a reception of a frame. Index k ranges between1 and K, whereas K represents the number of different frames that areincluded within a multi-frame. For simplicity of explanation only tworeceive MAC memory entry groups are illustrated (the first and the K'thMAC memory entry groups) but K can exceed two.

A typical receive frame access circuits (120″(k)) out of circuits120″(1)-120″(K) is adapted to repetitively generate a media memory unitaddress sequence that corresponds to the address of entries that form anassociated receive MAC memory entry group (150″(k)). The receive controlcircuit 110″ is adapted to select between the multiple receive frameaccess circuits 120″(1)-120″(K).

Conveniently, each receive MAC memory entry group (150″(k)) ends by anend of group indicator (EOGI) and the EOGI detector 140″ can detect anEOGI and in response notifies the receive control circuit 110″. Receivecontrol circuit 110″ can receive this indication as well as otherindications and can determine which is the next receive MAC memory entrygroup to scan.

First receive frame access circuit 120″(1) includes a first receive MACentry group address register 121″(1) that stores the address of thefirst entry of the first receive MAC memory entry group 150″(1). Thisaddress is sent to the receive control circuit 110″ whenever the receivecontrol circuit 110″ starts to scan the first receive MAC memory entrygroup 150″(1). The receive control circuit 110″ scans the first receiveMAC memory entry group by 150″(1) incrementing the addresses until theEOGI detector 140″ detects that the end of the first receive MAC memoryentry group 150″(1) was reached. Once it occurs the first receiverepetition counter 123″(1) updates its value to reflect that the firstreceive MAC entry group was scanned. The inventors used a count downcounter that its content was compared to zero (by zero detector 122″(1))to indicate that a predefined number of scans of the first receive MACmemory entry group was completed. Once the predefined number of scans iscompleted the first receive repetition counter 123″(1) is updated to theinitial predefined repetition number.

When the predefined number of scans of the first receive MAC memoryentry group 150″(1) is completed the second receive frame access circuit120″(2) is selected, and so on, until the K'th receive frame accesscircuit 120″(K) is selected by the receive control circuit 110″, and theK'th receive MAC memory entry group 150″(K) is scanned for a predefinednumber of times. After the K'th receive MAC memory entry group 150″(K)is scanned for a predefined number of times the reception of themulti-frame ends and the receive media access controller 264″ waits toreceive the next MFRAME_RX_SYNC1″ 192″.

The memory outputs reception instructions to the EOGI detector 140″ andto reception controller 160″. The EOGI detector 140″ looks for the EOGIfield, while the reception controller 160″ sends reception instructionsto the reception controller 160″.

The reception controller 160″ sends reception instructions to receptionpaths such as paths 281-284 and in response these reception pathsselectively receive information from the physical layer unit 290. Forsimplicity of explanation communication interface 170 and TMD ports 271were omitted from FIG. 9.

It is noted that the reception instructions sent to reception controller160″ can differ from the reception instructions sent by the receptioncontroller 160″ to the reception paths. For example, if the receptioncontroller 160″ is connected to each reception path via a dedicatedcontrol line the reception instructions sent by the reception controller160″ to the reception paths do not necessarily include reception pathidentification information while conveniently the reception instructionssent to the reception controller 160″ include such information. It isfurther noted that the changes can result from differences in the formatof the reception instructions. The reception controller 160″ can sendonly one reception instruction at a time but this is not necessarily so.The reception instructions can include reception start time information,although this is not necessarily so. Conveniently, a receptioninstruction defines the time slot allocated to each reception path.

According to an embodiment of the invention a scanning of a MAC memoryentry group is synchronized by a synchronization signalMFRAME_TX_SYNC1″.

FIG. 10 is a flow chart of method 300″ for receiving multi-frames,according to an embodiment of the invention.

Method 300″ starts by stage 310″ of providing a processor clock signalPR_CLK 196 to a processor and providing a communication line receiveclock signal LINE_RX_CLK1″ 191″ to a media access controller, such asreceive media access controller 264″.

Stage 310″ is followed by stage 330″ of writing, to the receive mediaaccess controller, multiple reception instructions that control areception of a multi-frame. These reception instructions define timewindows allocated to receivers.

Stage 330″ is followed by stages 350″ and 360″.

Stage 350″ includes scanning, during a single multi-frame period (thatconveniently starts by a multi-frame reception synchronization signalMFRAME_RX_SYNC1″), multiple receive MAC memory entry groups such as toretrieve reception instructions. A receive MAC memory entry group storesreception instructions that control a reception of a frame. During asingle multi-frame reception or more receive MAC memory entry groups arescanned multiple times.

Conveniently, stage 350″ includes stage 352″ of repetitively selecting aselected receive frame access circuit out of multiple receive frameaccess circuit. Each receive frame access circuit is adapted torepetitively generate a receive MAC memory unit address sequence thatcorresponds to address of entries of an associated receive MAC memoryentry group. Stage 352″ is followed by stage 354″ of scanning, inresponse to information provided by the selected receive frame accesscircuit, a selected receive MAC memory entry group.

Conveniently, stage 350″ includes searching for an end of groupindicator (EOGI) indicative of an end of a currently scanned receive MACentry group, and determining a next scanned receive MAC memory entrygroup in response to the detection of the EOGI.

Conveniently, stage 350″ includes timing a scanning of at least onereceive MAC memory entry group in response to a reception of anintra-multi-frame reception synchronization signal such asIFRAME_RX_SYNC1″ 199″ and detection of the EOGI.

Stage 360″ includes selectively receiving information from thecommunication line, in response to the retrieved reception instructions.

Conveniently, stage 360″ includes sending reception commands to multiplereception paths (also referred to as receivers) and allowing thesereceivers to receive information provided over the communication line.

Conveniently, stage 310″ also includes providing a processor clocksignal PR_CLK 196 to a second processor and providing a second receptioncommunication line clock signal LINE_RX_CLK2″ 197″ to a second receivemedia access controller. Stage 330″ of writing further includes writingto the second receive media access controller, multiple receptioninstructions that control a reception of a second multi-frame. Stage350″ of scanning further includes scanning, during a single multi-framereception period that starts by a second multi-frame receptionsynchronization signal MFRAME_RX_SYNC2″ 198″, multiple second receiveMAC memory entry groups such as to retrieve reception instructions.Stage 360″ further includes selectively receiving information from acommunication line, in response to the retrieved reception instructions.A second receive MAC memory entry group stores reception instructionsthat control a reception of a frame. During single multi-frame periodthe scanning includes scanning at least twice at least one receive MACmemory entry group.

FIG. 11 illustrates various stages 350″, 360″ of method 300″ forreceiving multi-frames, according to an embodiment of the invention.

Stage 350″ starts by stage 371″ of receiving MFRAME_RX_SYNC1″ 192″ andselecting a first selected receive MAC memory entry group. Index k andindex j are set to one. These indexes are used to repetitively scan thevarious receive MAC memory entry groups of the receive MAC memory unit.It is noted that index k can be set to another value, but it is assumed,for simplicity of explanation that the receive memory unit 150″ isarranged such that the receive MAC memory entries groups are arrange incorrespondence to the reception order, thus simplifying the jump processbetween the different receive MAC memory entry units and simplifying thedetermination of when the scan process ends.

Stage 371″ is followed by stage 373″ of reading the j'th entry of thek'th receive MAC memory entry group in synchronization withLINE_RX_CLK1″ 191″ and providing it to a reception controller. Theaccessed entry includes a reception instruction that is sent to thereception controller.

Stage 373″ is followed by stages 375″ and 361″. Stage 375″ includesdetermining if the j'th entry is the last entry of the k'th receive MACmemory entry group. If the answer is negative stage 375″ is followed bystage 376″ of increasing index j: j=j+1. Stage 376″ is followed by stage373″. Stages 373″-376″ scan the entire k'th receive MAC memory entrygroup.

If the answer is positive (the j'th entry of the k'th MAC memory entrygroup is the group) then stage 375″ is followed by stage 377″ of settingindex j to one. Stage 377 is followed by stage 379″ of determiningwhether to update k. The update can be responsive to the amount ofrepetition of the k'th frame that still needs to be transmitted. Ifindex k is not updated then the previously scanned receive MAC memoryentry group is scanned again. If the answer is positive then index k isupdated. It is noted that non-consecutive ordering of the receive MACmemory entry groups can cause index k to be updated in other manners.Assuming that there are K different frames within the multi-frame then kis updated such that after the K'th frames index k returns to one. Thisis illustrated by using a modulo operation: k=Mod_(K)|k+1|.

Stage 381″ is followed by stage 383: of determining if the multi-framereception ended. If the answer is positive then stage 383″ is followedby stage 371″, else it is followed by stage 373″.

Stage 373″ is followed by stage 361″ of providing the retrievedreception instruction to a selected receiver (or reception path) out ofmultiple receivers (or reception paths) and stage 363″ of receivinginformation in response to the reception instruction, by the selectedreceiver. Stage 363″ is followed by stage 383″.

According to an embodiment of the invention the scanning of a receiveMAC memory entry group can be synchronized with timing signals such asintra-multi-frame reception synchronization signal IFRAME_RX_SYNC″ 199″.Thus, stages 379″ and 381″ may be followed by stage 373″ only after sucha synchronizing signal is received. It is noted that the reception ofeach frame can be synchronized but this is not necessarily so.

Variations, modifications, and other implementations of what isdescribed herein will occur to those of ordinary skill in the artwithout departing from the spirit and the scope of the invention asclaimed. Accordingly, the invention is to be defined not by thepreceding illustrative description but instead by the spirit and scopeof the following claims.

1. A device, comprising: a processor coupled to a communication line viaa physical layer unit, the physical layer unit configured to generate acommunication line transmit clock signal and a multi-frame transmissionsynchronization signal; and a transmit media access controller (MAC)coupled to the physical layer unit wherein the transmit MAC isconfigured to receive the multi-frame transmission synchronizationsignal and the communication line transmit clock signal, and in responseto scan, during a single multi-frame transmission period, multipletransmit MAC memory entry groups within the transmit MAC to retrievetransmission instructions and in response to enable access to thecommunication line; wherein each transmit MAC memory entry group storestransmission instructions that control a transmission of a frame;wherein during the single multi-frame transmission period the transmitMAC accesses one transmit MAC memory entry group at least two times;wherein the processor is configured to generate the transmissioninstructions; and wherein the processor receives a processor clocksignal that differs from the communication line transmit clock signal.2. The device, according to claim 1 wherein the physical layer unit isconfigured to generate a communication line reception clock signal and amulti-frame reception synchronization signal; and wherein the devicecomprises a media access controller coupled to the physical layer unitwherein the MAC is configured to receive the multi-frame receptionsynchronization signal and the communication line reception clocksignal, and in response to scan, during a single multi-frame period,multiple receive MAC memory entry groups such as to retrieve receptioninstructions and in response selectively receive information from thecommunication line; wherein each receive MAC memory entry group storesreception instructions that control a reception of a frame; whereinduring a single multi-frame reception period the MAC accesses at leasttwice at least one MAC memory entry group; wherein the processor isconfigured to generate the multiple reception instructions; and whereinthe processor receives a processor clock signal that differs from acommunication line reception clock signal.
 3. The device according toclaim 2, wherein each transmit MAC memory entry group ends by an end ofgroup indicator (EOGI); and wherein the transmit MAC is configured tolocate a EOGI of a currently scanned transmit MAC memory entry group andin response to determine a next scanned transmit MAC memory entry group.4. The device according to claim 1 wherein each transmit MAC memoryentry group ends by an end of group indicator (EOGI), and wherein thetransmit MAC is configured to locate a EOGI of a current scannedtransmit MAC memory entry group and in response to determine a nextscanned transmit MAC memory entry group.
 5. The device according toclaim 4 wherein the transmit MAC comprises a transmit MAC memory unit, atransmit control circuit that scans the transmit MAC memory unit, and atransmission controller configured to control access to thecommunication line in response to the retrieved transmissioninstructions.
 6. The device according to claim 4 wherein the transmitMAC comprises multiple transmit frame access circuits wherein eachtransmit frame access circuit is configured to repetitively generate atransmit MAC memory unit address sequence that corresponds to address ofentries of an associated transmit MAC memory entry group; and whereinthe transmit control circuit is configured to select between themultiple transmit frame access circuits.
 7. The device according toclaim 4, wherein the device further comprises: a time slot assignercoupled to a second communication line via a second physical layer unit;the second physical layer unit configured to generate a secondcommunication line transmit clock signal and a second multi-frametransmission synchronization signal; a second transmit MAC configured toreceive the second multi-frame transmission synchronization signal andin response to scan, during a single multi-frame transmission period,multiple second transmit MAC memory entry groups such as to retrievetransmission instructions and in response to enable access to the secondcommunication line; wherein each second transmit MAC memory entry groupstores transmission instructions that control a transmission of a frame;and wherein during the single multi-frame transmission period the secondtransmit MAC accesses one transmit MAC memory entry group at least twotimes; and a second processor configured to generate the multipletransmission instructions; wherein the second processor receives aprocessor clock signal that differs from the second communication linetransmit clock signal.
 8. The device according to claim 7 wherein thesecond transmit MAC comprises a second transmit MAC memory unit, asecond transmit control circuit that scans the second transmit MACmemory unit, and a second transmission instruction controller,configured to control access to the second communication line inresponse to the retrieved transmission instructions.
 9. The deviceaccording to claim 8 wherein the second transmit MAC comprises multipletransmit frame access circuits, wherein each transmit frame accesscircuit is configured to repetitively generate a transmit MAC memoryunit address sequence that correspond to address of entries of anassociated second transmit MAC memory entry group and wherein the secondtransmit control circuit is configured to select between the multipletransmit frame access circuits.
 10. The device according to claim 4wherein the transmit MAC is coupled to multiple transmitters and whereinthe transmit MAC sends transmission commands to the multipletransmitters that determine an access of each transmitter to thecommunication line.
 11. The device according to claim 4 wherein thetransmit MAC is further configured to receive an intra-multi-frametransmission synchronization signal and to synchronize the scanning withthe intra-multi-frame transmission synchronization signal and themulti-frame transmission synchronization signal.
 12. The deviceaccording to claim 4, wherein a receive MAC comprises a receive MACmemory unit, a control circuit that scans the receive MAC memory unitand a reception controller, configured to control reception ofinformation from the communication line in response to the retrievedreception instructions.
 13. A method for transmitting multi-frames, themethod comprises: providing a processor clock signal to a processor andproviding a communication line clock signal to a transmit media accesscontroller (MAC); writing, to the transmit MAC, multiple transmissioninstructions that control a transmission of a multi-frame; and scanning,during a single multi-frame transmission period that starts by amulti-frame synchronization signal, multiple transmit MAC memory entrygroups within the transmit MAC to receive transmission instructions andin response to enabling access to the communication line; wherein atransmit MAC memory entry group stores transmission instructions thatcontrol a transmission of a frame; and wherein during the singlemulti-frame transmission period the scanning comprises scanning onetransmit MAC memory entry group at least two times.
 14. The methodaccording to claim 13, wherein the providing further comprises providingthe processor clock signal to a second processor and providing a secondcommunication line transmission clock signal to a second transmit mediaaccess controller MAC; wherein the writing further; comprises writing tothe second transmit MAC, multiple transmission instructions that controla transmission of a second multi-frame; wherein the scanning furthercomprises scanning during a single multi-frame transmission period thatstarts by a second multi-frame transmission synchronization signal,multiple second transmit MAC memory entry groups such as to retrievetransmission instructions and in response enabling access to the secondcommunication line; wherein a second transmit MAC memory entry groupstores transmission instructions that control a transmission of a frame;and wherein during the single multi-frame transmission period thescanning comprises scanning at least two times one transmit MAC memoryentry group.
 15. The method according to claim 13 wherein the scanningcomprises searching for an end of group indicator (EOGI) indicative ofan end of a currently scanned transmit MAC entry group; and determininga next scanned transmit MAC memory entry group in response to thedetection of the EOGI.
 16. The method according to claim 15 wherein thescanning comprises repetitively selecting a selected transmit frameaccess circuit out of multiple transmit frame access circuit; whereineach transmit frame access circuit is configured to repetitivelygenerate a transmit MAC memory unit address sequence that correspond toaddress of entries of an associated transmit MAC memory entry group; andscanning, by the selected transmit frame access circuit a selectedtransmit MAC memory entry group.
 17. The method according to claim 15,wherein the enabling comprises sending transmission commands to multipletransmitters and conveying information provided by the multipletransmitters to the communication line.
 18. The method according toclaim 15, further comprising timing a scanning of at least one transmitMAC memory entry group in response to a reception of anintra-multi-frame transmission synchronization signal.
 19. The methodaccording to claim 14, further comprising scanning, during a singlereceive multi-frame period that starts by a multi-frame receivesynchronization signal, multiple MAC memory entry groups such as toretrieve reception instructions and in response selectively receivinginformation from the communication line; wherein a receive MAC memoryentry group stores reception instructions that control a reception of aframe; wherein during the single multi-frame receive period the scanningcomprises scanning at least twice at least one receive MAC memory entrygroup.
 20. A method for transmitting multi-frames, the methodcomprising: providing a processor clock signal to a processor, andproviding a communication line clock signal to a transmit media accesscontroller (MAC); writing, to the transmit MAC, multiple transmissioninstructions that control a transmission of a multi-frame; and scanning,during a single multi-frame transmission period that starts by amulti-frame synchronization signal, multiple transmit MAC memory entrygroups such as to receive transmission instructions and in response toenabling access to the communication line; wherein a transmit MAC memoryentry group stores transmission instructions that control a transmissionof a frame; wherein during the single multi-frame transmission periodthe scanning includes scanning one transmit MAC memory entry group atleast two times; and wherein the scanning comprises searching for an endof group indicator (EOGI) indicative of an end of a currently scannedtransmit MAC entry group; and determining a next scanned transmit MACmemory entry group in response to the detection of the EOGI.